Truncation helps in the reduction of power consumption by disabling a portion of the partial product. In this paper different multipliers are made to truncate the partial products variably using a control bit and then compared for power and delay. High speed, Low power consumption, layout regularity, reduction in area, time and delay are the major concerns while implementing multipliers which represent the backbone of a DSP system. Multipliers developed are mainly of fixed width ie; for a N x N bit multiplication, the output attained is 2N bit product.
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Figure 4. Peres Gate PG. One of the efficient algorithms to handle such situation is the Baugh-Wooley multiplication. Let the numbers to be multiplied be A and B. As a first step pad each of the last two terms in the product P with zeros to obtain a 2n-bit number to aid adding it with the other terms. Let X be one of the last two terms that can represent it with zero padding as. Proposed Reversible Logic Gates In the block diagram shown in Figure 5 , three types of cells are used. The yellow cells represent the full adder.
Figure 5. Block diagram of 4-bit Baugh-Wooly multiplier. The grey cells represent the multiplier cell. Each of the multiplier cell receives four inputs namely, the multiplier input horizontal-green line , multiplicand input vertical-red line , carry from previous cells vertical-black line and sum from previous cells diagonal-black line. They produce two outputs namely sum output diagonal-black line and carry output vertical black line. In this work we are proposing two reversible multiplier cells representing black and grey cells.
Since each cell is having four inputs and two outputs, the reversible multiplier cell, in order to maintain the reversible constraints it is developed as a cell having five inputs and five outputs. Out of this, three outputs are maintained as garbage outputs. Out of the five outputs, two outputs Q and R are left unspecified, since these are the garbage outputs.
The functions S and T will produce sum and carry outputs respectively. The representation has the Gate Count of The Quantum cost is The number of two-Qubit gates is The functions S and T will produce sum and carry outputs respectively of the complement function of the Baugh- Wooley structure.
Figure 6. Reversible multiplier cell MC. Figure 7. Synthesis of reversible multiplier cell. These proposed multiplier cells are having one constant input. The input A is the multiplier bit. The input B is the multiplicand bit.
The input C is the carry input from the previous cells. The input D is the sum input from the previous cells. The outputs P, Q and R are considered as garbage outputs. Since this is an incompletely specified reversible logic gates the functions Q and R are not specified.
Results and Discussions The reversible multiplier designs available in the literature are for the array multipliers. There is no any specific application of any algorithm except .
However this work is compared and evaluated with the other array multiplier designs available in the literature. Therefore the proposed multiplier cells are evaluated based on the Gate count, Garbage inputs and Garbage outputs. Since the proposed cells are incompletely specified cells we could not generate the Quantum cost and therefore we could not evaluate the proposed gates based on the Quantum cost. In  , the design requires a total of 40 reversible gates,  requires 42, total number of gates required is 44 in  and in  the number of gates required is 32 gates.
The proposed Baugh-Wooley multiplier design requires 20 gates. Therefore, the hardware intricacy of the proposed design is less compared to the existing approaches. Constant Inputs One of the major factors in the design of a reversible logic circuit is the number of constant inputs.
The proposed reversible Baugh-Wooley multiplier design requires 16 constant inputs, but the design in   -  requires 52, 40, 44 and 42 respectively. Hence the proposed Baugh- Wooley Multiplier design is better than existing designs. Garbage Outputs The number of output of the reversible gate that is not making useful functions is referred as garbage output.
Other constraint in designing reversible logic circuit is optimizing garbage outputs. The proposed reversible Baugh- Wooley multiplier design produces 48 garbage outputs, but the design in   -  produces 52, 52, 40 and 49 garbage outputs respectively. Therefore, it is clear that this is the better design than the existing counterparts. The conclusion of the above discussion is that, it is evident that the proposed reversible Baugh-Wooley multiplier circuit design is better than the existing designs with respect to gate counts, garbage inputs and garbage outputs.
Evaluation of the Proposed Reversible Baugh-Wooley Multiplier Circuit The proposed reversible Baugh-Wooley multiplier circuit is more efficient compared to the existing circuits presented by   - .
This can be understood easily with the help of the comparison results shown in Table 1. These reversible multiplier cells are targeted for reversible Baugh-Wooley multiplier design. The proposed reversible multiplier cells are capable of multiplying 2 bits in the current array and add the result with the sum and carry outputs of previous array.
The Toffoli gate synthesis of the proposed reversible multiplier cell is also given. The functionality of the multiplier cell was verified with RC viewer. This design is useful in the multiplier design with reduced number of gates and constant inputs.
Even the proposed design is having moderate garbage outputs; we can conclude that this design is better in terms of number of gates and constant inputs. The number of gates, constant inputs and garbage outputs Figure 8. Complement reversible multiplier cell CMC.
Table 1. Comparison of proposed and existing design. It is comprehended that the number of gates, the constant inputs and garbage outputs values are fewer in number in the proposed design compared to the existing approaches. Conflicts of Interest.
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